Internet of Things Architecture (I
Author Contributions: Mateusz Komorkiewicz �� idea and design of OFHS hardware modules, design space exploration, final hardware system design and verification.Tomasz Kryjak �� preparing the previous works survey and tables, idea and design of pre-, post-filtering and reliability check modules, pointing out the improvements resulting in modified version.Marek Gorgon �� conception of FPGA pipelined processing system, evaluation of experiment with scientific trends, efficiency evaluation with GOPS, W, GOPS/W measures.* Author to whom correspondence should be addressed; E-Mail: lp.ude.hga@eikromok; Tel.: +48-12-617-3486; Fax: +48-12-634-1568.Author information ? Article notes ? Copyright and License information ?Received December 13, 2013; Revised January 20, 2014; Accepted January 23, 2014.
Copyright ? 2014 by the authors; licensee MDPI, Basel, Switzerland.This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/).AbstractThis article presents an efficient hardware implementation of the Horn-Schunck algorithm that can be used in an embedded optical flow sensor. An architecture is proposed, that realises the iterative Horn-Schunck algorithm in a pipelined manner. This modification allows to achieve data throughput of 175 MPixels/s and makes processing of Full HD video stream (1, 920 �� 1, 080 @ 60 fps) possible. The structure of the optical flow module as well as pre- and post-filtering blocks and a flow reliability computation unit is described in details.
Three versions of optical flow modules, with different numerical precision, working frequency and obtained results accuracy are proposed. The errors caused by switching from floating- to fixed-point computations are also evaluated. The described architecture was tested on popular sequences from an optical flow dataset of the Middlebury University. It achieves state-of-the-art results among hardware implementations of single scale methods. The designed fixed-point architecture achieves performance of 418 GOPS with power efficiency of 34 GOPS/W. The proposed floating-point module achieves 103 GFLOPS, with power efficiency of 24 GFLOPS/W. Moreover, a 100 times speedup compared to a modern CPU with SIMD support is reported.
A complete, working vision system realized on Xilinx VC707 evaluation board is also presented. It is able to compute optical flow for Full HD video stream received from an HDMI camera in real-time. The obtained results Drug_discovery prove that FPGA devices are an ideal platform for embedded vision systems.Keywords: FPGA, optical flow, Horn-Schunck, real-time systems, image processing, smart camera1.?IntroductionNowadays a continuous increase of vision sensors importance can be observed both in commercial and industrial applications.